1. Field of the Invention
The invention relates generally to error detection and correction circuitry for semiconductor memory devices, and more particularly, to automated, on-chip error detection for semiconductor chips containing multiple block memory arrays and correction thereof.
2. Description of the Prior Art
Recently, soft errors become a problem in a semiconductor memory device, wherein the information stored in a memory cell changes erroneously due to the entrance of .alpha. particles. The .alpha. particles are generated from radioactive materials included in the package material and the like. In order to solve the problem, an error check and correction (hereinafter referred to as ECC) function is provided on or external to the semiconductor memory device, whereby errors in information due to the soft errors are corrected. Consequently, the reliability of the semiconductor memory device can be enhanced.
The semiconductor memory device having the ECC function will be described in the following. FIG. 1 shows a structure of one example of a conventional semiconductor memory device having the ECC function. The semiconductor memory device comprises a write check bit generating circuit 1, a memory cell array 2, a read check bit generating circuit 5, a syndrome generating circuit 6, a syndrome decoder 7 and a data correction circuit 8. The memory cell array 2 comprises a data bit region 2 in which a plurality sets of data bits are stored and a check bit region 3 in which the corresponding plurality sets of check bits are stored. Each set of data bits comprises m bits and each set of check bits comprises k bits. Here, m is, for example, 16 and k is, for example, 6. Data bits and check bits are respectively inputted/outputted in parallel to and from the data bit region 3 and the check bit region 4 in accordance with an address signal.
The ECC function in the semiconductor memory device of FIG. 1 is generally effected in the following manner. In writing data, the write check bit generating circuit 1 generates a check bit having k bits based on a set of data bits having m bits in accordance with the structure of the error check and correction code. The check bits generated by the write check bit generating circuit 1 in this manner are called write check bits. The data bits and the write check bits are written in the data bit region 3 and the check bit region 4 of the memory cell array 2, respectively. A block of (m+k) bits consisting of a set of the data bits of m bits and a set of the check bits of k bits is called a ECC code word or simply an ECC word. The ECC code word is a unit in the error check and correction. Namely, the error check and correction are carried out for every ECC code word.
In reading data, a set of data bits of m bits and the corresponding set of write check bits of k bits are simultaneously read from the data bit region 3 and the check bit region 4, respectively, based on an address signal. The data bit is inputted to the read check bit generating circuit 5 and to the data correction circuit 8. The write check bits are inputted to the syndrome generating circuit 6 and to the data correction circuit 8. The read check bit generating circuit 5 generates a set of check bits of new k bits based on the inputted set of data bits of m bits in accordance with the structure of the error check and correction code. The check bits generated from the read check bit generating circuit 5 in this manner are called read check bits. The syndrome generating circuit 6 carries out exclusive OR operation for the write check bits read from the check bit region 4 and for the read check bits generated from the read check bit generating circuit 5, bit by bit. The result of the exclusive OR operation is called a syndrome. The syndrome is a data train consisted by k bits, comprising information indicating the location of the error bit. When all bits of the syndrome are "0", that is, when the write check bits and the read check bits coincide with each other, it is determined that there is no error and otherwise, it is determined that there is an error.
The syndrome having k bits generated from the syndrome generating circuit 6 is applied to the syndrome decoder 7. The syndrome decoder 7 generates a code of (m+k) bits which designates the error bit out of the set of data bits having m bits and the set of write check bits having k bits by decoding the syndrome of k bits. More specifically, it outputs a code in which only the position corresponding to the error bit becomes "1" and other positions become "0" in the (m+k) bits. The data correction circuit 8 inverts and therefore corrects one or a plurality of error bits from the data bits and the check bits read from the data bit region 3 and from the check bit region 4 in accordance with the (m+k) bit code. In this manner, the error check and correction of the data is effected. The error corrected (m+k) bits are written in the original position in the memory cell array 2.
Actually, the ECC circuit system such as described above is provided on the memory chip or out of the memory chip and the correction of errors due to the soft error is carried out by that ECC circuit system. In a semiconductor memory device having such ECC circuit system, not only the above described soft errors but also hard errors can be corrected. The hard error is a defect generated in manufacturing the memory chip and is a fixed error. The memory chip having a defect which can be corrected by the above mentioned ECC circuit system may be regarded as a sound chip. Therefore, by substantially repairing hard errors generated in manufacturing the memory chip by the ECC circuit system, especially on chip ECC, the production yield can be enhanced.
Now, the error check and correction code is capable of detecting an error if the number of error bits included in a unit of the above mentioned ECC code word (consisted by a set of data bits of m bits and a set of check bits of k bits in the above example) is p or less than p bits and it is capable of correcting an error if the number is 9 or less than q bits, where p&gt;q. Such error check and correction code is called a q bit error detection--p bit error correction code. Usually, a double error correction --triple error detection (DEC-TED) code, single error correction--double error detection (SEC-DED) code, and the like are used. In the following, description will be given of a case in which a defect (hard error) of a memory cell is repaired, that is, corrected, by employing the SEC-DED code, in order to simplify the description.
FIG. 2 shows the state of the bits selected by the address signals Ad1, Ad2 and Ad3, respectively. In FIG. 2, DB0 to DB7 denote data bits and CB0 to CB3 denote check bits. In this case, m=8 and k=4. More specifically, 12 bit data are simultaneously inputted or outputted in parallel in accordance with the inputted address signals Ad1, Ad2 and Ad3, respectively. The 12 bits corresponding to each of the address signals constitute an ECC code word. If an error of 1 bit exists in the ECC code word, the error can be corrected. In FIG. 2, a circle denotes a normal bit while x denotes a defective bit. When there is 1 bit error or no bit error in the 12 bits selected by each of the address signal, as shown in FIG. 2, the error can be corrected by the SEC-DED code. The semiconductor memory device including such defective bit can be regarded as a sound device provided that it comprises the ECC function employing the SEC-DED code.
Next, description will be given of a case in which the defective bits are distributed as shown in FIG. 3. Referring to FIG. 3, two defective bits are included in the 12 bits selected by the address signal Ad1. These two defective bits can not be corrected by the ECC function employing the SEC-DED code. Therefore, although there are no defective bits included in the respective 12 bits selected by other address signals Ad2 and Ad3, there is an error which can not be corrected when viewed as a whole. Therefore, the memory chip including such defective bits is regarded as a defective one.
As described above, not the number of the defective bits in the memory cell array but the distribution of the defective bits has a large influence of the lowering of the production yield. For example, when parallel data of 12 bits are inputted or outputted, the memory cell array is usually divided into a plurality of blocks in some way or another and data of one or a plurality of bits are inputted or outputted to or from each block. A common address signal (a row address signal and a column address signal) is inputted to these blocks. The address signal is decoded by a decoder, whereby the memory cell corresponding to the address signal is selected. In FIG. 4, the memory cell array is divided into three blocks 2a, 2b and 2c. 4 bits of a set of data bits are stored in the block 2a, another 4 bits of a set of data bits are stored in the block 2b and a set of check bits having 4 bits is stored in the block 2c.
Since a conventional semiconductor memory device having the ECC function is structured as described above, the production yield may be significantly lower dependent on the distribution of the defective bits (address position) even if the total number of the defective bits is small.
In IBM' Technical Disclosure Bulletin Vol. 26, No. 6, Nov. 1983, pp. 2747-2748, a following description is disclosed:
"In the design of fault tolerant memory using fault alignment exclusion-inclusion techniques, if a chip with a bit line fail aligns with another chip with a word line fail, then the memory produces a memory word with a 2-bit error. If the memory is equipped with SEC/DED code, then through address translation these two chips are misaligned so that the memory word in the reconfigured memory has only a 1-bit error. Such a reconfiguration using address translation alone limits the number of bit line, word line and cell fails which can be dispersed."
To our knowledge, however, the above described technique is not suitable for automated testing of multiple block memory array of a single chip and according to such technique, it is virtually impossible to implement an external program such as a laser melting program.